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Research Papers

A Semantic Association Hardware Acceleration System for Integrated Product Data Management

[+] Author and Article Information
J. Lane Thames1

 School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332lane.thames@gatech.edu

Oliver Eck

 Department of Computer Science, HTWG, Konstanz, D-78462, Germanyeck@htwg-konstanz.de

Dirk Schaefer

 Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332dirk.schaefer@me.gatech.edu

1

Corresponding author.

J. Comput. Inf. Sci. Eng 12(3), 031009 (Aug 31, 2012) (11 pages) doi:10.1115/1.4007405 History: Received June 03, 2012; Revised August 02, 2012; Published August 31, 2012; Online August 31, 2012

Many modern products are complex systems comprised of highly integrated mechanical, electrical, electronic, and software components, which are commonly known as mechatronic systems. Similarly, product data and life-cycle management systems that support the engineering and design of mechatronic systems are becoming complex and need to store, retrieve, and process vast amounts of files associated with mechatronic products. For many years, software developers and computer architects have benefited by continuous increases in computational performance, as predicted by Moore’s law. However, issues such as extreme power consumption have begun to limit certain types of performance increases such as hardware clock rates. In an effort to find new ways to increase computational performance, engineers and computer scientists have been investigating new techniques such as hardware acceleration systems, reconfigurable computing, and heterogeneous computing (HC). In light of these emerging computational paradigms, this paper introduces a semantic association hardware acceleration system for integrated product data management (PDM) based on semantic file systems. The concept of semantic path merger (SPM) is described along with a discussion of its realization as a hardware-based associative memory for accelerated semantic file retrieval. The energy and retrieval performance metrics of the proposed hardware system is given along with its comparative analysis with the industry standard content addressable memory (CAM). The goal of the proposed system is to enhance the state-of-art for the field of heterogeneous computing within the scope of computational platforms for design and engineering applications.

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Copyright © 2012 by American Society of Mechanical Engineers
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References

Figures

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Metadata extraction system

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Figure 2

Generic trie-to-hardware mapping technique

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Figure 3

Three prefix subtries representing the reference labels R1,R2, and R3 from Table 2

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Figure 4

The hypergrid illustrating semantic path merger and semantic coloring of prefix paths

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Block diagram illustrating a hardware-based implementation of the SPM algorithm

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Figure 6

Comparing EPO versus (N, w, c) for the SPM algorithm and the content addressable memory

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Comparing TPO versus (N, w, c) for the SPM algorithm and the content addressable memory

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Figure 8

Comparing EDP versus (N, w, c) for the SPM algorithm and the content addressable memory

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Figure 9

Comparing dynamic power versus (N, w, c) for the SPM algorithm and the content addressable memory

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Figure 10

Comparing static power versus (N, w, c) for the SPM algorithm and the content addressable memory

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Figure 11

Comparing total power versus (N, w, c) for the SPM algorithm and the content addressable memory

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